entity AtlasRODFormatter

Packs readout data according to ATLAS ROD-readout format and SLINK-standard.

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Used Packages

ieee.std_logic_1164 all
EXEMPLAR.EXEMPLAR_1164 all
lpm.lpmdeclarations all
CSLIB.cslibdeclarations all

Generics

WITH_BUS_ANALYZER STRING := "NO"
ANALYZER_FIFO_DEPTH POSITIVE := 256
VME_WIDTH POSITIVE := 32
WITH_DATA_COUNTER STRING := "YES"
CANDIDATE_COUNTER_WIDTH POSITIVE := 8
CANDIDATE_WIDTH POSITIVE := 23
FORMAT_ID std_logic_vector(31 downto 0) := X"00000001"
DETECTOR_ID std_logic_vector(31 downto 0) := X"74010101"
EVENT_TYPE std_logic_vector(31 downto 0) := X"00000000"

Ports

clock in std_logic
sclr in std_logic
ignoreSlinkStatus in std_logic := '0'
generateEmptyEvent in std_logic := '0'
DAQActive in std_logic
StartEvent in std_logic
MoreCandidates in std_logic
CandidateValid in std_logic
readNextCandidate out std_logic
Candidates in std_logic_vector(CANDIDATE_WIDTH-1 downto 0)
EVID in std_logic_vector(23 downto 0)
BCID in std_logic_vector(11 downto 0)
TriggerType in std_logic_vector( 7 downto 0)
StatusFlags in std_logic_vector(31 downto 0)
ErrorFlags in std_logic_vector(31 downto 0)
CandidateCount in std_logic_vector(CANDIDATE_COUNTER_WIDTH-1 downto 0)
DataSent out std_logic
AnalyzerMode in std_logic := '0'
AnalyzerContineousMode in std_logic := '1'
VmeData out std_logic_vector(VME_WIDTH-1 downto 0)
advanceAnalyzerFifo in std_logic := '0'
readAnalyzerFifo0 in std_logic := '0'
readAnalyzerFifo1 in std_logic := '0'
readAnalyzerFifo2 in std_logic := '0'
readAnalyzerFifo3 in std_logic := '0'
readAnalyzerFifoLow in std_logic := '0'
readAnalyzerFifoHigh in std_logic := '0'
lff in std_logic
ldown in std_logic
ureset out std_logic
utest out std_logic
uctrl out std_logic
uwen out std_logic
ud out std_logic_vector(31 downto 0)

Architectures

AtlasRODFormatter_arch1

Detailed Description

This entity can be used in order to drive a 32 bit duplex SLINK source card with Atlas readout data formatted according to the Atlas ROD format specified in "The event format in the ATLAS DAQ/EF prototype-1" (Atlas Daq note 50: ATL-DAQ-98-129).

The variable data which are placed into the various fields of the Header, Data section and Trailor of the format are provided to the entity via various input ports.

The following restrictions / features are provided:

The format is "hardcoded" to a variable length data-section but exactly two status words.
The status words are provided after the data-section.
FORMAT_ID, DETECTOR_ID, EVENT_TYPE can be changed via generics.
It is possible to either use an internal data counter in order to determine the length of the data section, or to provide this length externally.
It is possible to implement a Bus-Analyzer which permits to dump the outgoing data into a Fifo which afterwards can be read out. This option is very valuable for debugging purposes. Two operation modes exist: The first samples the output lines to the SLINK every 25 ns, whereas the second one writes only valid data (uwen=0) to the Analyzer Fifo. The mode can be changed via an input signal. With the program SlinkAnalyzerFormatter a dump of the Fifo can be transformed into a graphical representation. An example for this can be found among the diagrams.
The Formatter can be told to ignore the SLINK flow control. This can be used for example to test the system without a functional SLINK connected to the board.
Via an input port the Formatter can be told to generate an empty event. This can be used in case of internal errors in the system and avoids that meaningless data is propagated through the system using up bandwidth. In all cases the status words are correctly transferred.

Examples of usage and diagrams of some formats can be found in the links below.

This entity has been developed for the MUCTPI interface. Therefore some names have meanings which refer to the MUCTPI context: The meaning of VME-Bus is actually some internal data bus via which readout actions can be performed. Candidates are the actually the Data you want to transfer to the SLINK. A Candidate takes one data word.

Generics:

WITH_BUS_ANALYZER	determines if a Bus Analyzer will be implemented or not (to save resources). (possible values : "YES / NO")
ANALYZER_FIFO_DEPTH	gives the depth of the analyzer fifo in words (40 bits wide).
VME_WIDTH	is the width of the internal data bus which is used to readout the analyzer-fifo. YOU MUST USE EITHER 8 OR 32 BITS.
WITH_DATA_COUNTER	decides if an internal counter is implemented in order determine the length of the data section. If this information is already present in the design and can be provided via a port to the AtlasRODFormatter you can save resources by non implementing the counter (possible values: "YES / NO").
CANDIDATE_COUNTER_WIDTH	has to be adjusted according to the maxmimal possible length of the data section.
CANDIDATE_WIDTH	is the width of the data words you want to send to the SLINK via the AtlasRODFormatter. If your words are less wide than 32 bits you can save resources.

Ports:

clock	is usually 40 MHz.
sclr	is a general reset.
ignoreSlinkStatus	if '1' ignores lff and ldown of SLINK.
generateEmptyEvent	if '1' generates event with empty data section
DAQActive	must be '1' in order to activate the readout process.
StartEvent	is the trigger to start the readout. It has to asserted until DataSent goes to '0' which indicates that the Controler STM has started (usually it starts only if the SLINK is ready to receive data).
readNextCandidate	indicates that the user should provide the next Candidate at the data input.
MoreCandidates	is needed by the internal state machine. It must indicate if there are more data words in the chain after the current Candidate for the current event. It serves as a "data-look-ahaead" bin and optimizes the Formatter for speed.
CandidateValid	indicates that the Candidates port contains valid data which must be read in by the Formatter.
Candidates	is the data input.
EVID	needs to be provided to form the header.
BCID	needs to be provided to form the header.
TriggerType	needs to be provided to form the header.
ErrorFlags	contains the first status word.
StatusFlags	contains the second status word.
CandidateCount	needs to be provided only if no internal Candidate Counter is implemented.
DataSent	indicates that the previous event has been sent and that the Formatter is ready for the next event.
AnalyzerMode	switches on the filling of the Analyzer Fifo.
AnalyzerContineousMode	If '1' at each clock cycle a data word is written into the fifo. In this case the readout is triggered by 'StartEvent'. If '0' only valid data (uwen='0') is written into the fifo.
VmeData	via this port the Analyzer fifo is read out.
advanceAnalyzerFifo	increments the readpointer of the Analyzer Fifo by one during the next clock.
readAnalyzerFifo0	if 8 bit VmeData : reads out byte 0
readAnalyzerFifo1	if 8 bit VmeData : reads out byte 1
readAnalyzerFifo2	if 8 bit VmeData : reads out byte 2
readAnalyzerFifo3	if 8 bit VmeData : reads out byte 3
readAnalyzerFifoLow	if 32 bit VmeData : reads out 32 bit data from AnalyzerFifo.
readAnalyzerFifoHigh	reads out the controlbits from the AnalyzerFifo. The following bit mapping holds: bit 0: ureset, bit 1: utest, bit 2: uctrl, bit 3: uwen, bit 4: lff, bit 5: ldown, bit 6: AnalyzerFifoEmpty, bit 7: AnalyzerFifoFull.
lff	SLINK line
ldown	SLINK line
ureset	SLINK line
utest	SLINK line
uctrl	SLINK line
uwen	SLINK line
ud	SLINK line

Diagrams : , ,

Version: $Revision: 1.14 $
Date: $Date: 2000/10/12 11:38:24 $
Author: Christoph Schwick
Generated: schwick@dsy-srv2 on Wed Oct 18 15:23:21 200.