Package Documentation

entity PowerUpReset

generates a reset pulse at power-up.

Used Packages

ieee.std_logic_1164 all
exemplar.exemplar_1164 all

Ports

clock in std_logic
trigger in std_logic
reset out std_logic

Architectures

PowerUpReset_arch1

Detailed Description

This small entity only serves to generate a three clock cycles long pulse at power up. Afterwards the output will be always zero.

Ports:

can be used to trigger a clear at another time than at power up. It could come from a ReadWritePulseDecoder.

Version: $Revision: 1.4 $
Date: $Date: 2000/10/12 11:38:24 $
Author: Christoph Schwick
Generated: schwick@dsy-srv2 on Wed Oct 18 15:23:21 200.