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entity SlinkInterface

Provides 32 bit interface to the SLINK.

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Detailed Description

The Interface contains a mechanism that ensures that after a reset the StopTransfer signal remains asserted for 3 more clock cycles. If the logic before the SlinkInterface detects the falling edge of the StopTransfer signal and immediately sends data they arrive only 4 clocks after the ldown signal of the slink has been deactivated. This is the required timing for the SLINK specification. In the current implementation the utest port is hold at '0'.

Ports:

lfflink full flag
ldownlink down signal
udSLINK data bus
uresetSLINK reset input
utestSLINK test input
uctrlSLINK control word input (to be asserted if a control word is to be transferred)
uwenSLINK write enable
crtluser data is control word
datauser data input to the interface
data_validuser data valid
stopTransferat maximum two more words may be written to the link