entity pipeline

Delays data words for a fixed number of clocks.

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Used Packages

ieee.std_logic_1164 all
exemplar.exemplar_1164 all

Generics

WIDTH positive := 32
DEPTH positive := 4

Ports

data in std_logic_vector(WIDTH-1 downto 0)
q out std_logic_vector(WIDTH-1 downto 0)
clock in std_logic
enable in std_logic := '1'
aclr in std_logic := '0'
sclr in std_logic := '0'

Architectures

pipeline_lpm_arch

Detailed Description

The pipeline can be used to keep data during a period in which part of it is processed by other hardware components. Two architectures are available: pipeline_lpm_arch is based on the lpm_shiftreg library components whereas pipeline_arch1 is composed of single flip-flops.

Generics:

WIDTH	is the width of the data word.
DEPTH	is the number of clocks (flip-flop layers) after which the input appears at the output.

Ports:

sclr	is usable only in the pipeline_lpm_arch.
ena	is usable only in the pipeline_lpm_arch.

Version: $Revision: 1.8 $
Date: $Date: 2000/10/12 11:38:24 $
Author: Christoph Schwick
Generated: schwick@dsy-srv2 on Wed Oct 18 15:23:21 200.